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| TK75018 SWITCHED CAPACITOR VOLTAGE CONVERTER WITH REGULATOR APPLICATIONS s s s s Voltage Inverter Negative Voltage Doubler Voltage Regulator Positive Voltage Doubler TK75018 FB/SD CAP + V+ FEATURES s s s s s 35 mA (typ.) Output Current Operating Range 3.5 to 7 V Reference and Error Amplifier for Regulation External Shutdown External Oscillator Synch OSC DESCRIPTION The TK75018 is a monolithic switched capacitor converter with feedback control. With just two capacitors, the TK75018 can create a negative voltage supply which tracks a positive supply. As an alternative, the feedback pin can be used to establish regulation at a desired voltage, and it can also be used as a shutdown signal input. A single TK75018 can also be configured as a non-inverting step-up converter or dual output voltage doubler. With no external timing elements, the converter will selfoscillate at 25 kHz, nominal. This frequency can also be user adjusted with a small capacitor or synchronized to another oscillator. Quiescent current is typically 2.5 mA. Standby current is guaranteed less than 200 A over the full operating temperature and input voltage ranges. GND CAP - Vref VOUT FB/SD CAP + V+ OSC GND CAP - Vref VOUT FB/SD NC CAP+ GND NC CAPNC V+ NC OSC Vref NC NC VOUT BLOCK DIAGRAM V+ DRIVE Vref BANDGAP REFERENCE 1.25 V + DRIVE FB/SD CAP + ORDERING INFORMATION TK75018 Package Code C OSC OSC CONTROL Q VOUT Q DRIVE CAP - Tape/Reel Code Temp. Range GND DRIVE PACKAGE CODE D: DIP-8 M: SOP-8 V: TSSOP-14 TEMPERATURE RANGE C: -20 TO 80 C TAPE/REEL CODE TL: Tape Left May 1999 TOKO, Inc. Page 1 TK75018 ABSOLUTE MAXIMUM RATINGS Supply Voltage VIN For Doubler Conf. ....................... 7 V Supply Voltage VIN For Regulating Conf. .................. 8 V Power Dissipation TK75018M (Note 1) .............. 600 mW Power Dissipation TK75018D (Note 2) ............ 1000 mW Power Dissipation TK75018V (Note 3) .............. 950 mW Storage Temperature Range ................... -55 to +150 C Operating Temperature Range ..................... -20 to 80 C Junction Temperature .......................................... 150 C Lead Soldering Temperature (10 s) ..................... 235 C TK75018 ELECTRICAL CHARACTERISTICS Test conditions: VIN = 5.0 V, TA = Tj = Operating Temperature Range, Note 6 Configuration, unless otherwise specified. SYMBOL ICC(Reg) ICC(Inv) V CC V LOSS ROUT fOSC V ref V OUT Line Reg PARAMETER Supply Current Regulating Supply Current Inverting Mode Supply Voltage Range Voltage Loss (VIN - VOUT) Output Resistance Oscillator Frequency Reference Voltage Regulated Voltage Line Regulation TEST CONDITIONS ILOAD = 0 mA, (Note 6) ILOAD = 0 mA Under Note 6 Conditions IOUT = 1 mA, (Note 4) IOUT = 20 mA, (Note 4) IOUT = 1 mA to 20 mA, (Notes 4,5) 3.5 V VIN 7 V, (Note 6) TA = Tj = 25 C TA = Tj = Operating Temp. Range Tj = 25 C, I L = 1 mA, (Note 6) 3.5 V VIN 7 V, IL = 1 mA, (Note 6) 1 mA IOUT 20 mA, (Note 6) 1 mA IOUT 35 mA, (Note 6) V PIN1 = 0 V, (Note 6) V ref 80 A 15 2.35 2.25 -2.8 -3.0 15 20 60 60 350 3.5 0.35 1 32 25 2.50 MIN TYP 2.5 3.5 MAX 3.5 4.5 7 0.55 1.5 54 35 2.65 2.75 -3.2 80 150 300 200 UNITS mA mA V V V kHz V V V mV mV mV A LoadReg 1 Load Regulation @ 20 mA LoadReg 2 Load Regulation @ 35 mA ISTBY ROUT(Ref) Note 1: Note 2: Note 3: Note 4: Note 5: Standby Current Reference Output Resistance Power dissipation is 600 mW when mounted as recommended. Derate at 4.8 mW/C for operation above 25 C. Power dissipation is 1000 mW when mounted as recommended. Derate at 8 mW/C for operation above 25 C Power dissipation is 950 mW when mounted as recommended. Derate at 7.6 mW/ C for operation above 25 C. Device is connected as an inverter, with pins 1, 6, and 7 unconnected; CIN = 2.2 F tantalum, COUT = 33 F tantalum. Output resistance means the slope of the VOUT vs. IOUT curve, for output currents of 1 to 20 mA. This represents a linear approximation of the curve. Note 6: Device is connected as a positive to negative converter/regulator with R1 = 44.2 k, R2 = 154 k, C1 = 4.7 nF, CVIN = 4.7 F tantalum, CIN = 2.2 F tantalum, COUT = 33 F tantalum. Page 2 May 1999 TOKO, Inc. TK75018 TEST CIRCUITS VIN = 3.5 TO 7 V VIN = 3.5 to 6 V V+ + 4.7 F CAP + CIN 2.2 F + GND CAP - VOUT COUT 33 F + VOUT FB/SD V+ 4.7 F + + CIN 2.2 F CAP + R1 GND Vref R2 CAP - VOUT VOUT COUT 33 F 0.002 F + NOTE 4 TEST CIRCUIT (Non Regulating) NOTE 6 TEST CIRCUIT (Regulating) TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT VOLTAGE REGULATING @ 0 mA LOAD VS. TEMPERATURE -2.8 OUTPUT VOLTAGE REGULATING @ 20 mA LOAD VS. TEMPERATURE -2.8 -2.8 -2.85 -2.90 -2.85 -2.9 VOUT (V) OUTPUT VOLTAGE REGULATING @ 35 mA LOAD VS. TEMPERATURE VOUT REGULATING MODE -2.85 -2.9 -2.95 -3.0 -3.05 -3.1 -3.15 -3.2 -50 0 VIN = 5 V -3.0 -3.05 -3.1 VOUT (V) Note 6 Test Circuit -2.95 -2.95 -3.0 -3.05 -3.1 -3.15 -3.2 -50 0 Note 6 Test Circuit 50 100 Note 6 Test Circuit 50 100 -3.15 -3.2 -50 0 50 100 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) OUTPUT VOLTAGE VS. OUTPUT CURRENT -2.8 OUTPUT VOLTAGE VS. TEMPERATURE -3.4 VOUT (V) NON REGULATING VOLTAGE LOSS VS. OUTPUT CURRENT VLOSS (V) NON REGULATING VOUT REGULATING MODE (V) -2.85 -2.90 -2.95 -3.0 -3.05 -3.1 -3.15 -3.2 0 10 20 VIN = 5 V CIN = 2.2 F COUT = 33 F -3.6 -3.8 -4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -50 0 IL = 5 mA Note 4 Test Circuit 50 100 IL = 20 mA 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 CIN = 2.2 F COUT = 33 F VIN = 5 V Tj = 25 C Note 6 Test Circuit 30 40 Note 4 Test Circuit 4 8 12 16 20 24 28 32 36 IOUT (mA) IOUT (mA) TEMPERATURE (C) May 1999 TOKO, Inc. Page 3 TK75018 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) SUPPLY CURRENT vs. TEMPERATURE @ 5 V 3 SUPPLY CURRENT VS. INPUT VOLTAGE 30 3 IL = 0 IIN(AVE) (mA) AVERAGE INPUT CURRENT VS. OUTPUT CURRENT 2.8 ICC (mA) 2.6 2.4 2.2 Note 6 Test Circuit 2 -50 ICC (mA) 20 2 1 Note 6 Test Circuit 0 0 50 100 10 Note 6 Test Circuit 0 0 6 VIN (V) 12 0 15 IOUT (mA) 30 TEMPERATURE (C) STANDBY CURRENT VS. TEMPERATURE 100 90 80 70 STANDBY CURRENT VS. INPUT VOLTAGE 120 100 ISTBY (A) 0.6 STANDBY THRESHOLD VS. TEMPERATURE VPIN1 = 0 V VPIN1 VTH(SA) (V) 0.4 ISTBY (mA) 60 50 40 30 20 10 0 -50 0 Note 6 Test Circuit 80 60 40 Note 6 Test Circuit 20 0 6 VIN (V) 12 0.2 Note 6 Test Circuit 0 -50 0 50 100 50 100 TEMPERATURE (C) TEMPERATURE (C) MAXIMUM SWITCH CURRENT vs. TEMPERATURE 105 100 2.65 2.60 REFERENCE VOLTAGE VS. TEMPERATURE 35 OSCILLATOR FREQUENCY VS. TEMPERATURE Vref (V) 95 90 85 CAP+ Current to GND 80 -50 0 50 100 2.50 2.45 2.40 2.35 -50 Note 6 Test Circuit 0 50 100 fOSC (kHz) ISW (mA) 2.55 25 VIN = 5 V Note 6 Test Circuit 15 -75 -25 25 75 125 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) Page 4 May 1999 TOKO, Inc. TK75018 TYPICAL PERFORMANCE CHARACTERISTICS (CONT.) OUTPUT VOLTAGE LOSS VS. OSCILLATOR FREQUENCY INVERTER CONFIGURATION 2.0 C = 2.2 F TANTALUM IN COUT = 33 F TANTALUM VLOSS (V) VLOSS (V) OUTPUT VOLTAGE LOSS VS. OSCILLATOR FREQUENCY INVERTER CONFIGURATION 2.0 C = 22 F TANTALUM IN COUT = 33 F TANTALUM VLOSS (V) 1.0 0.8 0.6 0.4 0.2 OUTPUT VOLTAGE LOSS VS. INPUT CAPACITOR INVERTER CONFIGURATION COUT = 33F TANTALUM fOSC = 25 kHz IOUT = 10 mA 1.0 IOUT =10 mA 1.0 IOUT =10 mA Note 4 Test Circuit 0 1 10 fOSC (kHz) 100 0 1 Note 4 Test Circuit 10 fOSC (kHz) 100 0 0 20 Note 4 Test Circuit 40 60 80 100 CIN (F) THEORY OF OPERATION As in any switched capacitor converter, the means of conveying energy from input to output is done by charging a capacitor between two potentials and then switching one end of the capacitor to a different potential. By some means of rectification, the other end of the capacitor is then forced to dump charge into another capacitor at the converter output, thereby conveying energy. In a simple example shown in Figure 1, a capacitor C1 has one side tied to ground and another side charged by a voltage source of potential V1. The non-grounded side of C1 is then switched over to be connected to one side of a capacitor C2, which is at potential V2 and referenced to ground. V2 represents the output of the converter. The initial charge on C1 is: q 1 = C1 x V1 When the switch changes over to the V2 side, C1 is discharged from potential V1 to potential V2. After discharge has occurred the charge on C1 is then: q 2 = C1 x V 2 This means that the net transfer of charge which has occurred is: q = q1 - q2 = C1 (V1 - V2) REQUIV = (V1 - V2) / IL = 1 / (O x C1) V1 fO IL C1 C2 V2 FIGURE 1: SWITCHED CAPACITOR CIRCUIT If the potential V2 is sourcing a current IL, the charge will have to be delivered at a rate: O = IL /q = IL / C1(V1 - V2) Thus, the higher the frequency, the more current that can be supported by the converter output. All else being ideal, the effective losses in the converter in the energy conveyance process is identical to that of a circuit consisting of a resistor between the potentials V1 and V2, with the same load at the output side. This equivalent resistor is simply: May 1999 TOKO, Inc. Page 5 TK75018 THEORY OF OPERATION (CONT.) The illustration in Figure 2 represents an equivalent circuit to the basic example of a switched capacitor circuit in Figure 1. V1 REQUIV IL C2 V2 Using equalities established above we find: = V2 / V1 = {V1 - [IL / (O x C1)]} / V1 = 1 - [IL / (O x C1 x V1)] The last term in the equality string shows that efficiency can be improved by increasing frequency or the value of C1. Limitations of the circuit and components tend to cause losses which increase with increasing frequency. Therefore, at some point in the frequency spectrum losses will be minimized. Hence, the oscillator of the TK75018 is designed to run in the frequency band where losses are minimized. Since the user will primarily be interested in maintaining a given output voltage, losses are characterized in terms of the voltage loss. FIGURE 2: SWITCHED CAPACITOR EQUIVALENT CIRCUIT The efficiency of the ideal converter is given by the output power divided by the input power. Since the same current flows out of each potential, the efficiency, , is equal to the ratio of V2 to V1. PIN DESCRIPTIONS FEEDBACK AND SHUTDOWN (FB/SD) By configuring an error voltage divider into the FB/SD pin, the TK75018 can be used to regulate the output voltage. It is recommended that the parallel combination of the divider resistors be greater than approximately 16 k due to the limited current available from the reference. The Error Amplifier compares the FB/SD pin against an internal 1.25 V reference and limits the charge rate of CIN, thereby limiting its peak charged voltage over a given clock period and, thus, lowering the charge delivery rate to the output. The characteristic frequency response of the converter can be tailored by adjusting the ratio of COUT:CIN, but it is recommended to keep it around 10:1. A "lead" capacitor from the negative output to the feedback input is required to maintain good light-load regulation; 2000 pF is recommended, regardless of output voltage. For standard configurations, the magnitude of the regulated voltage must be less than that which can be achieved without regulation, |VOUT| - VLOSS. Higher regulated output voltages can be achieved by configuring a voltage doubler, at the expense of maximum available output current. When the FB/SD pin is pulled below the shutdown threshold of ~0.45 V (e.g., via an open collector of an NPN transistor), the reference is shut off and the switching action is terminated. The drivers are set to allow both CIN and COUT to discharge into the output load. The quiescent supply current will drop to ~ 60 A. If an error voltage divider is not Page 6 being used, the TK75018 will automatically restart when the shutdown signal is removed. If such a divider is being used, the current through the divider may be sufficient to keep the device in shutdown until COUT is fully discharged, since the reference to the amplifier has collapsed during the shutdown. Although COUT is discharged fairly quickly (allowing a quick restart), this recycling delay may not be acceptable in some applications. This recycling delay can be bypassed by injecting a positive start-up pulse into the SD/FB pin (see Figure 3). This might be readily configured, for example, as a TTL level signal which is diode coupled into the divider. A resistor should be chosen to limit the voltage pulse injection magnitude to 0.7 to 1.1 V. A pulse width of 100 s is required to guarantee a successfully coupled start-up signal. + VIN 4.7 F V+ FB/SD RESTART CAP + + Vref R2 CIN 2.2 F TANTALUM CAP - VOUT GND + R1 SHUTDOWN COUT 33 F TANTALUM VOUT FIGURE 3: FEEDBACK AND SHUTDOWN May 1999 TOKO, Inc. TK75018 PIN DESCRIPTIONS (CONT.) INPUT CAPACITOR CHARGING PINS (CAP+/CAP- ) The positive driving pin of CIN (CAP +) charges the positive node of the capacitor to VIN during tCH and pulls it down to ground during t DIS. The negative driving pin of C IN (CAP -) pulls the negative node of the capacitor to ground during tCH and is driven into the output during tDIS. CIRCUIT GROUND (GND) All potentials are referenced to this ground unless otherwise noted. OUTPUT VOLTAGE (VOUT) In most applications, a capacitor must be placed from this pin to ground to integrate the charge pulses delivered by CIN. A minimum of ten times CIN is recommended. Since the output voltage serves as the substrate inside the IC, the design must ensure that this pin is never raised to a higher potential than ground. This phenomenon will tend to occur when a positive-supply-to-negative-supply load is present at the converter output. A circuit, such as the one shown in Figure 4, is recommended. Under normal operation, the transistor will appear as a short circuit. But the sink current will be cut off from the output pin if the voltage starts to approach ground. The resistor is chosen to keep the transistor saturated under all steady-state operating conditions. V+ IL LOAD REFERENCE VOLTAGE (Vref) This pin provides a nominal 2.5 V buffered reference for external use. Normal output current should be kept below ~160 A. OSCILLATOR PROGRAMMING (OSC) This pin can be used to alter the nominal 25 kHz frequency of the internal oscillator. An internal timing capacitor of ~150 pF is alternately charged during tCH and discharged during tDIS with a 7 A current source to fixed threshold levels. Adding an external capacitor from the OSC pin to ground will parallel the 150 pF capacitor to slow down the clock period. Adding a small external capacitor from the OSC pin to the CAP+ pin will source/sink extra charge into/ out-of the internal timing capacitor to speed up the transition between thresholds and thereby raise the oscillator frequency. It is recommended that, in the latter configuration, the capacitor be kept below ~30 pF. Synchronization of multiple TK75018s can be accomplished by adding pull-up resistors from the OSC pin to the reference voltage and using an open collector from an NPN transistor to provide the discharge. The NPN is then driven by a clocking pulse, and the same pulse can be used to drive multiple devices in the same configuration. It is not recommended to pull the OSC pin high with a lowimpedance source. To synchronize and regulate with multiple devices, an external reference can be used as the reference point for the error voltage divider, thus allowing the internal reference to be used as the pull-up point for the OSC pin. INPUT VOLTAGE (V+) The input voltage is used to charge CIN during the time tCH during each clock period. CIN is then discharged into the output capacitor during time tDIS. During tCH, the input current will be approximately 2.2 times the output current. During tDIS, the input current will be approximately 0.2 times the output current. A low ESR bypass capacitor will average out the varying current seen by the input supply yielding an average input current of approximately 1.1 times the output current. The bypass capacitor should be placed as near to the TK75018 as possible to disallow inductive spikes on the supply rail of the IC. A minimum of 2 F is recommended. V+ CAP + + CIN GND CAP - VOUT COUT + FIGURE 4: POSITIVE REFERENCED LOAD The equation below can be used to calculate the values of the feedback resistors (R1 and R2) needed to achieve a desired output voltage. R2 = R1 ( |V V| +1) where R 24 k 1.2 OUT 1 May 1999 TOKO, Inc. Page 7 TK75018 PACKAGE OUTLINE 0.76 1.27 SOP-8 8 5 TSSOP-14 e1 5.4 0.35 3.9 e 1.27 Marking Recommended Mount Pad AAAAA 1 4 0.5 4.89 0 ~ 10 YYY 4.4 e 0.65 Recommended Mount Pad + 0.3 1.45 1.64 0.2 1 6.07 + 0.3 7 Lot. No. 0.42 1.27 0.1 0.12 l 0 ~ 0.25 e 0.9 Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) 1.2 max 0.50 0 ~ 10 5.0 4.8 0 ~ 0.15 0.1 6.4 + 0.3 14 8 1.0 DIP-8 8 5 Marking Lot Number 0.25 +0.15 -0.15 e 0.65 0.12 6.4 M Country of Origin Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) 1 4 9.5 3.3 3.8 + 0.3 Marking Information Product Code 0.25 + 0.15 - 0.05 e1 0.5 min 3.3 + 0.3 TK75018 7.62 0 ~15 e 2.54 0.46 + 0.15 - 0.05 0.25 M Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified) Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 TOKO AMERICA REGIONAL OFFICES Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375 Visit our Internet site at http://www.tokoam.com The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc. Page 8 (c) 1999 Toko, Inc. All Rights Reserved IC-xxx-TK75018 0798O0.0K May 1999 TOKO, Inc. Printed in the USA 0.15 +0.15 -0.15 |
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